The phase-locked loop (PLL) is a versatile electronic circuit used in a wide variety of applications, including frequency synthesis, clock recovery, clock multiplication, and clock regeneration. In large, high-speed integrated circuits (including application-specific integrated circuits, field-programmable gate arrays, network processors, and general purpose microprocessors), PLLs have become commonplace. On-chip phase-locked loop clock multipliers are used on these chips to generate a high-frequency clock signal that is a multiple of, and in phase with, a system clock or I/O clock. PLLs may also be used on these chips to resynchronize and realign clocks in deep clock distribution trees to reduce clock skew.
FIG. 1 illustrates an example block diagram of a PLL 100. The PLL 100 includes a phase-frequency detector (PFD) 110, a charge pump (CP) 120, a filter (e.g., low pass filter (LPF)) 130, and an oscillator 140. The output frequency of the oscillator 140 is controlled by one or more input control signals. In operation, the PLL 100 adjusts the oscillator 140 to match (in both frequency and phase) a reference input 160. The PLL 100 may also include a divider 150 on a feedback loop from the oscillator 140 to the PFD 110. The divider 150 takes PLL output 165 and divides it by N so that the divided signal 170 is compared to the reference input. This enables the PLL output 165 to be N times higher in frequency than the reference input 160, allowing the PLL 100 to perform frequency multiplication.
A self-biased PLL (SBPLL) is used to create on-chip PLLs that have low jitter and are relatively insensitive to integrated circuit process variations, supply voltage and operating temperature (PVT). However, a major weakness of the SBPLL is that the oscillator output is subject to amplitude variability and common mode disturbances during dynamic operation of the PLL (e.g., acquisition, locking). In particular, operational correction can lead to the front-end oscillator amplifier and the following amplifying stages (the so-called “post-oscillator amplifiers”) being biased out of their optimal range (sweet spot), causing pulse evaporation (truncation, or dropped output clocks) and functional failure. This problem manifests as a non-monotonic montonic oscillator control surface (output frequency versus control inputs) which may lead to one or more of the following: long lock time or lock failure due to positive feedback, sensitivity to power supply noise, and functional sensitivity to large reference and/or feedback clock noise.